timing signoff

Back in Cycle 1, when you ran static timing analysis on the synthesized netlist, you were timing the chip on paper. The clock tree was still an ideal assumption, the wires were rough estimates, and a single "typical" set of conditions stood in for the whole factory. It is like checking whether a road trip fits in a day using a straight-line map and good weather: useful for planning, but not a promise. Timing signoff is the moment you redo that same analysis on the real, fully built layout — with the actual routed wires, the real clock tree, and every operating condition the part will ever see — and only then declare "this will work in silicon." It is the final gate before tapeout, the answer to "will it really run?" rather than "should it run?"

What makes it trustworthy is what you feed it. After routing, an extraction tool reads the finished geometry and computes the parasitic resistance and capacitance of every wire — how long each metal segment is, how wide, which layer, and which neighbors run alongside it coupling charge across the gap — and writes it out, typically as a SPEF file. The timer combines those real RC delays with the cell delays from the standard-cell libraries and recomputes setup and hold slack on every path. Crucially, it does this across all corners and all modes at once: corners are the physical extremes (slow/fast silicon, low/high voltage, cold/hot — slow-slow at low voltage hurts setup, fast-fast hurts hold), and modes are the functional states (mission mode, test/scan, low-power). The cross-product of corners and modes is the multi-mode multi-corner (MMMC) view, and a path must pass in every cell of that grid, because the chip has to work in all of them.

On top of the corners, signoff adds margin for effects an idealized run ignored: on-chip variation derating (OCV, and its sharper successors AOCV and POCV) so that two gates side by side aren't assumed to be identically fast, plus crosstalk delay from switching neighbors, IR-drop-aware delay from a sagging power grid, and clock jitter. Any path that still shows negative slack here is a real silicon risk, fixed with a timing ECO — a surgical resize, buffer, or reroute that must not break the corners that were already passing. Sign-off is reached only when worst negative slack is zero or better across the entire MMMC space; that, together with clean DRC and LVS, is what lets the design go to GDSII.