process corner (PVT)

No two chips off the line are identical, and none of them runs in a perfectly controlled room. The transistors come out a little faster or a little slower than the textbook value (that's the manufacturing spread), the supply voltage sags or spikes a bit, and the silicon runs anywhere from freezing cold to scorching hot. A process corner is a deliberately pessimistic recipe that pins all three of those knobs to a worst-case (or best-case) setting at once — Process, Voltage, Temperature, hence PVT — and says: the chip must still work here. Think of it like stress-testing a bridge not at the average traffic load but at the heaviest truck on the hottest day with the cheapest batch of steel. If it survives the corners, you trust it survives everything in between.

The corners get short names from how the transistors turn out. SS means slow-slow silicon (slow NMOS and slow PMOS), FF means fast-fast, TT is the typical center, and SF / FS describe skewed cases where one transistor type came out fast and the other slow. You pair each with a voltage and a temperature. The intuition for which corner bites: setup checks (is the data fast enough to arrive before the clock edge?) are usually worst in the slow, low-voltage corner because everything is sluggish; hold checks (does the data stay put long enough?) are usually worst in the fast, high-voltage corner because signals race ahead. Temperature used to be simple — hotter meant slower — but at modern low-voltage nodes that can invert, so cold silicon is sometimes the slow case. That is exactly why you don't reason about one corner by hand; you let the tool sweep all of them.

Checking one corner at a time would take forever and miss interactions, so signoff uses MMMC — multi-mode multi-corner. A mode is an operating scenario the chip runs in (normal function, scan test, a low-power sleep state, a turbo state), and each mode cares about a different clock and constraint set. MMMC builds the full grid of every mode crossed with every relevant corner and analyzes them together in one run, after routing, with the real extracted parasitics in the timing model. Closing timing means there is no failing path in any cell of that grid — only then has the design genuinely met timing across the whole envelope of silicon, supply, and temperature it will ever face.