parasitic extraction

When you draw a schematic, a wire is just a line with no cost — a perfect connection that delays nothing. Real metal is not so generous. Every wire on the finished layout has resistance, because metal isn't a perfect conductor, and capacitance, because it sits next to other wires and over the silicon, and any two conductors separated by an insulator store charge. Parasitic extraction is the step where the tool walks over the routed layout, looks at the exact geometry of every wire — its length, width, which metal layer it's on, what neighbors run alongside it — and computes those hidden R and C values. Nothing about the chip changes; extraction only measures what the routing already built. The result is a parasitics file, usually in the vendor-neutral SPEF format (Standard Parasitic Exchange Format), that lists the resistance and capacitance of every net so the timing tools can stop guessing and start using the truth.

This matters because those parasitics are what actually make signals slow. A driver has to charge up the capacitance of the wire through the wire's own resistance before the far end sees the new value, and the delay of a long, thin wire grows roughly with the square of its length — double the wire and you can quadruple its delay. Before routing exists, timing tools work from estimates (a wire-load guess, or a quick virtual route); after extraction, they swap in numbers derived from the real shapes, which is why post-route timing is the timing you trust. Extraction also captures the capacitance between a wire and its immediate neighbors, the coupling that lets one switching wire disturb another — the raw material for crosstalk and signal-integrity checks later in signoff.

Under the hood there's a speed-versus-accuracy dial. The gold standard is a field solver, which solves the electromagnetics of the 3D metal geometry almost exactly but is far too slow to run on a whole chip. So production tools mostly use rule-based or pattern-matching extraction: the foundry pre-characterizes thousands of common wire-and-neighbor configurations with a field solver, and the tool recognizes those patterns in your layout and looks up the answer. You reserve the slow, exact field-solver runs for the handful of critical or unusual nets where getting the number slightly wrong could sink your timing.