routing

Once placement has parked every cell in its spot on the silicon, routing is the step that actually draws the metal wires joining them — the physical interconnect that carries each signal from a driving pin to the pins it feeds. Picture a city where all the buildings are already built and you now have to lay every road and pipe connecting them, except you can't just pave at street level: a chip stacks many metal layers on top of each other (often a dozen-plus), and to keep wires from crashing into each other, neighboring layers run in alternating preferred directions — one layer mostly horizontal, the next mostly vertical, like a multi-storey road grid where each floor only runs one way. The lowest, thinnest layers handle short, dense local hops; the higher, thicker layers carry the long cross-chip hauls and power.

Routers do this in two passes because solving it all at once would be hopeless. First, global routing carves the die into a coarse grid of rectangular tiles and decides, for each net, roughly which tiles it should pass through and how many wires want to cross each tile boundary — a capacity-planning sketch that flags where too many wires are fighting for too little room (congestion) before a single real wire exists. Then detailed routing commits to the exact geometry: it snaps each net onto specific routing tracks and legal segments on each layer, obeying the foundry's width and spacing rules so the result will pass DRC. Whenever a wire has to move from one layer to another — say from a horizontal layer up to a vertical one — the router drops a via, a tiny conductive plug through the insulation that stitches the two layers together; a long signal may climb up several layers and back down through a whole stack of vias on its journey.

Vias and the metal itself are not free: each adds resistance and capacitance, so a path forced onto thin lower layers or pushed through many vias gets slower, which is exactly why routing can make or break the timing that placement and clock-tree synthesis set up earlier. After routing finishes, the tool extracts the real resistance and capacitance (RC) of these drawn wires and re-runs static timing analysis on the actual geometry — the first time your timing reflects physical wires rather than estimates — followed by DRC and LVS checks before the layout heads toward tapeout.