place and route
Place and route is the step where a chip stops being a wiring diagram and becomes a physical object. You start with a netlist — a list of pre-designed standard cells (AND gates, flip-flops, each with a fixed layout) and which pins connect to which. "Place" decides where each cell sits on the silicon die; "route" draws the metal wires that join them across stacked metal layers. Think of laying out a city: first you position thousands of tiny buildings, then you pave roads on multiple levels so every building can reach the others without gridlock.
Tools like Innovus or OpenROAD do this automatically, but "automatic" hides a brutal optimization. Cells that talk a lot should sit close, or wire delay blows your timing; pack them too tight and the router can't fit the wires, or the power density creates hotspots. So the engine juggles timing, area, power and routability at once, across millions of cells. The output is the GDSII layout — the exact polygons the foundry turns into photomasks, which a lithography tool then prints onto the wafer.
A common confusion: place-and-route doesn't invent your logic — that came earlier from synthesis, which mapped your RTL (Verilog) into standard cells. P&R only decides geography and wiring. Yet geography is destiny: at advanced nodes, wire delay often rivals or exceeds gate delay, so where a cell lands can matter more than how fast the cell itself switches. That's why timing closure — endlessly nudging placement and routing until no path is too slow — eats most of a back-end engineer's schedule.