register-transfer level (RTL)
Register-transfer level, or RTL, is the level at which engineers actually "write" a chip. Instead of drawing millions of individual transistors, you describe the chip's behavior as data flowing between storage cells called registers — what gets computed, and where it lands on each tick of the clock. It feels like coding: you write logic in a hardware description language such as Verilog or VHDL, much as a programmer writes software — except every line describes real hardware.
The key idea is the clock. On each clock edge, registers snapshot their inputs and hold them steady; between edges, combinational logic crunches those values to prepare the next snapshot. So an RTL line like `q <= a + b` means "on the next tick, register q takes the sum of a and b." You check the design by simulation, then a synthesis tool translates it down into a netlist of actual logic gates and flip-flops — the bridge from your code to silicon.
A common confusion: RTL is neither the lowest level nor the highest. Above it sit behavioral modeling and high-level synthesis (describing intent in C-like code); below it sit gate-level and transistor-level. RTL became the industry's center of gravity in the 1990s precisely because logic synthesis grew good enough to turn it into gates automatically — letting designers think in clock cycles and data flow instead of wiring up gates by hand.