metal layer (BEOL)

Once the transistors are etched into the silicon, they're useless until you wire them together — and a modern chip has billions of them. You can't do that on one flat surface any more than a city could connect every building with a single street. So the foundry builds a stacked road network in the layers above the transistors: a dozen or more sheets of metal wiring, stacked one atop the next, with insulator between them and tiny vertical elevators called vias punching through to connect a wire on one level to a wire on the next. This whole metal stack is the back-end-of-line, or BEOL — "back end" because it's fabricated after the transistors themselves (the front-end-of-line), layer by layer, on top of them. When place-and-route "routes," these are the layers it's drawing wires on.

The layers are deliberately not all the same. Down near the transistors, the lowest metals (often called M1, M2, and up) are thin and packed at a fine pitch — narrow alleys for short, local hops between neighbouring cells, where you need density far more than speed. Climb the stack and the wires get progressively wider and thicker, ending in fat top-level metals reserved for two jobs: carrying clean power and ground across the whole die (the power delivery network), and ferrying long-distance signals from one side of the chip to the other. The reason is plain resistance. A wire's resistance is R = rho*L/A — proportional to its length and inversely proportional to its cross-sectional area — so a long run on a thin lower layer would be hopelessly resistive and slow; promote it to a thick upper layer with a big cross-section and the resistance per millimetre drops sharply. That's why a good router sends short nets down low and long or power-hungry nets up high.

These copper wires aren't ideal, though: each one carries real resistance and forms capacitance with its neighbours and the layers above and below. Those parasitics are exactly what extraction pulls out of the finished layout and hands to static timing analysis, because at advanced nodes the delay of the metal can rival or exceed the delay of the gates it connects. So the metal stack isn't just plumbing you bolt on at the end — which layer a net rides on, and how the layers are sized, is a first-class design decision that shapes whether the chip meets timing and survives its power demands.