clock tree synthesis (CTS)

Picture a garden where every plant must get watered at the exact same instant. If you run one hose to the nearest plant and let the water trickle onward to the far corners, the close plants drink first and the distant ones drink late. So instead you build a branching manifold of equal-length pipes, splitting again and again, so the water reaches every sprinkler head at nearly the same moment. Clock tree synthesis (CTS) does this for the clock signal. After placement has fixed where every cell sits, the clock still arrives at the source as a single net that, left alone, would fan out wildly unevenly to thousands or millions of flip-flops. CTS rips out that naive net and rebuilds it as a balanced tree of clock buffers and inverters, sized and positioned so the active clock edge lands at every flip-flop's clock pin at almost the same time. A common structure is the H-tree, where the wire literally branches in nested H shapes so each leaf is the same distance from the root.

Two numbers describe how well the tree is balanced. Insertion delay (also called latency) is how long the edge takes to travel from the clock source down through all those buffers to a flip-flop. Skew is the spread in arrival times across the flip-flops you care about: if one flop sees the edge at 1.10 ns and another at 1.13 ns, the skew between them is 30 ps. You cannot make insertion delay zero, since buffers and wire take real time, but you fight to keep skew small, because timing closure depends on it. The setup check is how much time data has to arrive before the next clock edge, and the hold check is making sure data does not arrive too soon after the current edge. Skew shifts those edges around relative to each other, so a sloppy tree can manufacture timing violations that no amount of faster logic will fix.

CTS runs after placement and before detailed routing, and it is a balancing act in more than one sense. Bigger buffers and more balancing levels cut skew but burn dynamic power, since every one of those buffers toggles on every cycle, and a clock network is often among the largest power consumers on the die. Tools also build in margin for on-chip variation (OCV), the reality that two identical buffers in different corners of the chip switch at slightly different speeds because of voltage droop and process spread, so a tree that looks perfectly balanced in nominal conditions still needs slack to survive the real silicon. Modern flows often relax the old goal of near-zero global skew in favor of useful skew, deliberately delaying some flops to borrow time for tight paths, but the underlying job is unchanged: tame one clock so it reaches the whole sea of flip-flops together enough to meet timing.