slack

Imagine you have to be at the airport gate by 3:00, and you actually stroll up at 2:48. Those twelve spare minutes are your cushion — miss a turn or hit a slow line and you're still fine. In chip timing, slack is exactly that cushion, measured in fractions of a nanosecond: it's how much spare time a signal has when it arrives at its destination compared to the deadline it had to meet.

More precisely, every path between two registers has a required time (the latest the signal is allowed to arrive and still be safely captured on the next clock edge) and an arrival time (when the signal actually shows up after rippling through the logic). For a setup check, slack is just the difference: required minus arrival. Positive slack means the signal beat the deadline with room to spare — the path passes. Zero slack means it arrives at the very last instant. Negative slack means it's late: the data hasn't settled by the time the clock tries to grab it, so the path fails timing and the chip won't run reliably at that clock speed.

Slack is the headline number that static timing analysis reports for every path in the design, and the path with the worst (smallest) slack is the critical path — the bottleneck that sets your maximum clock frequency, whether that worst slack is barely positive or deep in the red. The whole game of timing closure is hunting down negative-slack paths and fixing them: speeding up slow logic, resizing cells, restructuring the path — or, if the target was simply too aggressive, relaxing a timing constraint (which lowers the frequency you're signing off at) until every path lands at zero or above. Engineers talk about the worst negative slack (WNS) for the single worst path and total negative slack (TNS) for the summed shortfall across all failing endpoints.