static timing analysis (STA)

Imagine you want to know whether a courier can carry a package across a city and arrive before a deadline — every single time, on every possible route. One way is to dispatch couriers all day and watch the clock, but you would never cover every street. The smarter way is to grab the map, add up the worst-case travel time on each road segment for every route, and check that even the slowest route beats the deadline. Static timing analysis (STA) does exactly this for a chip: instead of running simulation with test vectors, it walks every path that a signal can travel — from one register to the next — and adds up the delays along the way, then confirms each path finishes in time.

Concretely, STA breaks the design into timing paths, each starting at a launching register and ending at a capturing one. For each path it sums the delay of every standard cell the signal passes through plus the delay of the wires connecting them. It then runs two checks against the clock: a setup check, that data launched on one clock edge arrives before the next edge — with a little margin left for the register's setup time and for clock uncertainty; and a hold check, that data does not arrive too soon and overwrite the value the same edge is still capturing. STA reports the margin on each check as slack, and any path with negative slack is a violation. Because it is "static," it never needs input stimulus — it reasons about the timing graph directly, so it can guarantee EVERY path is covered, which simulation can never promise.

The point of all this is to pin down how fast the chip can legally run. The slowest setup path — the critical path — sets the floor on the clock period: the period can be no shorter than that path's delay plus the capturing register's setup time and the clock uncertainty. The maximum frequency is the inverse of that minimum period. Shave delay off the critical path and the whole chip can be clocked faster; miss the budget on even one path and the part fails at speed. This is why STA is the gatekeeper of timing sign-off — the final check that every path, fast and slow alike, lands inside its window before a design is declared safe to build.