timing constraint (SDC)
Imagine handing a courier a parcel and saying "this has to arrive by 9:00 sharp." You're not telling the courier which roads to take — you're stating the deadline, and it's their job to find a route that meets it. A timing constraint is exactly that kind of instruction, but aimed at your chip-design tools. You tell them how fast the clock ticks and what the deadlines are, and they go figure out the gates and wiring that hit those deadlines.
The most important thing you declare is the clock period — say, "this clock runs at 1 GHz, so a signal has roughly 1 nanosecond to travel from one register to the next." From that single statement the tools derive a timing budget for the paths in the design. They then lean on it twice: synthesis uses it to pick faster or smaller gates so the logic fits the budget, and static timing analysis uses it afterward to check that nothing arrives late (setup) — or, just as bad, too early (hold). Without constraints the tools have no deadline to aim at, and "is this chip fast enough?" becomes an unanswerable question.
Beyond the clock itself, you also describe the world outside your block — how much of the period is already used up by upstream logic before a signal reaches your input (input delay), and how much time the next chip downstream still needs after your output (output delay) — and you carve out exceptions for paths that don't play by the normal rules: a false path that never logically propagates and shouldn't be timed at all, or a multicycle path you deliberately allow two or more clock ticks to complete. In practice all of this is written in SDC (Synopsys Design Constraints), a Tcl-based text format that nearly every vendor's tools read, so the same intent survives as your design moves from one tool to the next.
# 1 GHz clock on port clk; data_in already consumes 0.3 ns upstream before it arrives create_clock -name clk -period 1.0 [get_ports clk] set_input_delay 0.3 -clock clk [get_ports data_in]
A minimal SDC snippet — define a 1 ns clock, then declare how much of that period is spent outside the block before an input arrives.
"SDC" is often used as a synonym for "timing constraints," but they aren't quite the same thing: SDC is the file format (born at Synopsys), while the timing constraint is the underlying intent — the clock and budget — that the file happens to encode. The same intent can also be expressed in a tool's native commands; SDC just makes it portable.