logic synthesis
Think about translating a recipe written in plain English ("whisk the eggs until fluffy, fold in the flour") into precise robot-arm instructions a factory machine can actually execute. You wrote the intent at a high level; something has to turn it into concrete physical steps. Logic synthesis is that translator for chips. You describe what your circuit should do in RTL — Verilog, SystemVerilog, or VHDL that talks about registers, arithmetic, and "if this, then that" — and the synthesis tool works out how to build it out of real hardware.
More precisely, logic synthesis takes your register-transfer-level description and compiles it into a gate-level netlist: a wiring diagram listing specific logic cells (AND gates, multiplexers, flip-flops, and so on) and how they connect. But it can't pick just any cells — it draws only from a standard-cell library, a fixed menu of pre-designed, pre-characterized gates that the foundry guarantees it can manufacture on a given process node. The tool maps your logic onto that menu, then optimizes hard: it factors out shared terms, merges redundant logic, and resizes gates to trade off speed, area, and power against your goals.
The catch is that the tool can't optimize blindly — it has to honor your timing constraints, chiefly the clock period every path must beat. Using delay numbers from the characterized library (plus estimated wiring delay), synthesis reshapes the combinational logic — and sometimes restructures it across register boundaries, a step called retiming — so the slowest path still settles within one clock period. Get this right and you hand off a netlist that's meant to be functionally equivalent to your RTL but ready for the next stage, place and route, where those cells get physical locations on the die. Synthesis is where an abstract design first becomes a real, buildable circuit.
assign sum = a + b;
Write `assign sum = a + b;` in RTL and you've said nothing about how to add. Synthesis turns that one line into a concrete adder built from library cells — a ripple-carry chain if area is tight, or a faster carry-lookahead structure if that path is struggling to meet the clock — and wires it up for you.
"Synthesis" sounds like it builds something from nothing, but the work is mostly the opposite — narrowing the huge space of possible implementations down to one good netlist. Note the boundary: classic logic synthesis only estimates wire delay from statistical wire-load models; the real interconnect delay isn't known until place and route lays down physical wiring, which is why modern flows increasingly blur the two stages with "physically aware" synthesis. (The promise that the netlist truly matches your RTL is then confirmed separately by formal equivalence checking.)