power intent

Power intent is the formal, machine-readable description of how a chip's power is meant to be managed — which blocks can switch off, what voltages they run at, and exactly what protective cells guard their boundaries. The catch it solves: standard RTL (Verilog/VHDL) describes only what the logic does, not how it is powered. A multiplier 'works' identically whether or not its domain can be switched off — the supply structure is simply invisible to the logic description.

Power intent fills that gap in a separate side-file that lists power domains, supply nets, power switches, isolation cells, level shifters, and retention strategies, plus the legal voltage states and the save/restore and power-up sequences. Every tool in the flow — synthesis, place-and-route, simulation, and verification — reads this same file so they all agree on the power architecture. The two industry formats are UPF (the IEEE 1801 standard, Tcl-based) and Synopsys's earlier CPF; getting the power intent right is as critical as the RTL itself, since a single missing isolation cell can corrupt the chip on wake-up.