Low-power design & UPF

retention register

A retention register is a flip-flop with a tiny always-on memory cell bolted on, so that when its block is powered down, it can save its current bit and instantly restore it on wake-up — like jotting your page number on a bookmark before you put the book away. Without it, powering down a domain erases all its state, forcing a slow full reboot of that block every time it wakes.

Inside, the main flop runs on the switchable supply, while a small low-leakage 'balloon' latch runs on the always-on supply. A save signal copies the bit into the balloon just before power-off; a restore signal copies it back the instant power returns. This costs extra area and a little always-on leakage, but it lets a domain drop into deep sleep and resume in nanoseconds with its registers, counters, and configuration intact. The designer marks which registers must retain in the power-intent file; only the truly stateful ones are made retention cells, since each one is bigger and leakier than a plain flop.

save → power-off → ... → power-on → restore

Retention is the middle ground between full power-off (state lost, lowest leakage) and clock gating (state kept, full leakage); it pairs naturally with isolation cells and a defined save/restore sequence in UPF.

Also called
state-retention flopballoon latch保留正反器狀態保留暫存器