power gating
Clock gating quiets a block by holding its clock still, but the transistors are still connected to the supply, so they keep sipping a trickle of current even while idle. Power gating goes all the way: it flips the block's power switch fully OFF, like cutting the breaker to an empty wing of a house instead of just turning the lights off. With no supply rail energized, the idle logic stops leaking, which directly attacks leakage (static) power — the steady drain that flows just because transistors are powered up, and that has grown into a huge slice of a chip's total power at modern nodes.
The switch itself is a row of big transistors inserted between the real, always-on supply and the block's own local rail (the layout calls these virtual VDD or virtual ground). A header switch is a PMOS device sitting between VDD and the block's virtual VDD; a footer switch is an NMOS device between the block's virtual ground and true ground. When you assert the sleep signal, those switches turn off and the local rail floats, so almost no current flows. Two companions make this safe in practice: isolation cells clamp the now-floating outputs of the sleeping block to a known 0 or 1 so neighbors don't see garbage, and retention registers (or a save-and-restore scheme) hold the handful of state bits you must not lose, since cutting power otherwise wipes everything.
Power gating is one tool in a low-power toolbox. Multi-Vt design mixes in high-threshold cells that leak far less (at the cost of switching a bit slower) on paths that have timing slack to spare, while DVFS — dynamic voltage and frequency scaling — dials the supply voltage and clock frequency up or down to match the workload and so trims dynamic, switching power. Because all of this changes which parts of the chip are powered when, the design's power intent (where the domains are, which switches feed them, what to isolate, what to retain) is written up front in a UPF (IEEE 1801) or CPF file that the whole back-end flow — synthesis, place, CTS, route, and verification — reads and enforces.
Why off-switching and high-V_t cells both matter: leakage scales with supply voltage but explodes as the transistor threshold drops at smaller nodes, so cutting V_DD to zero (power gating) or raising V_t (multi-Vt) each slash that static drain.
Power gating is not free: the switch transistors cost area and add a small IR drop in series with the block, waking a domain takes time and an inrush current spike, and you only come out ahead if the block stays asleep long enough to repay that overhead — so it's reserved for blocks with genuinely idle modes, not anything that toggles constantly.