clock gating

Picture a big office building where the rule is that every light must blink on and off in lockstep, all day, in every room, even the empty ones. That blinking costs electricity whether anyone is using the room or not. Clock gating is the building manager walking down the hall and flipping off the master switch to whole wings that nobody is in. In a chip, the flip-flops are the rooms and the clock is the relentless blink: on every clock edge a flip-flop re-evaluates its input, and that re-evaluation jiggles transistors and charges and discharges wires. If a block of logic isn't doing anything useful this cycle, you don't want its clock arriving at all. So you insert a small gating cell that, when an enable signal says 'idle,' stops the clock from reaching that group of flops. Their outputs freeze, nothing downstream toggles, and the dynamic power those flops and their fanout would have burned simply doesn't get spent.

Why does stopping the toggling save so much? Dynamic power, the energy spent actually switching signals back and forth, follows P = alpha * C * V^2 * f, where C is the capacitance you charge and discharge, V is the supply voltage, f is the clock frequency, and alpha is the activity factor, the fraction of cycles a node actually flips. The clock net is the busiest, highest-alpha signal on the whole chip because by definition it toggles every single cycle, so it and the flops it drives dominate dynamic power. Killing the clock to an idle region drives alpha toward zero there, and because the term is linear in that activity (and in f and C) the savings are large and direct. Note this attacks dynamic power only; the leakage current that trickles through transistors even when they're not switching is untouched, and for that you reach for power gating instead.

In practice you rarely hand-build the AND gate yourself, because a naive 'AND the clock with enable' can produce glitches or clip the clock pulse if enable changes at the wrong moment. Instead the synthesis tool inserts a purpose-built integrated clock-gating cell (an ICG), typically a latch-based design that samples the enable on the inactive phase of the clock so the gated output is always a clean, full-width pulse or a clean steady level. Tools do this automatically when you let them: RTL written as 'update this register only when enable is true' gets recognized and converted into a gated clock, and during physical design the clock-tree synthesis step then balances and buffers the clock through those ICG cells so the enabled paths still arrive on time.