power delivery network (PDN)

Think of the chip as a tall apartment building where every room needs water at full pressure, all at once. The power delivery network is the plumbing: the mesh of metal wires that carries the supply voltage (VDD) and the return path to ground (VSS) from the chip's edge pins down to every single standard cell, so each transistor gets the clean voltage it needs to switch. You start building this skeleton at floorplan time, before a single logic cell is placed — because once the core fills up with cells, there is no room left to run fat power wires, just as you can't add a water main after the walls are up and the rooms are furnished.

Picture the geometry in layers. Thin horizontal rails run in the lowest metal directly over each row of standard cells, alternating VDD and VSS so a cell can tap power right above it. Those rails feed up through stacked vias to wider, lower-resistance straps in the upper, thicker metal layers, which cross the die in a regular grid — vertical stripes over horizontal stripes — often ringed around the whole core. The result is a redundant mesh with many parallel paths, so current to any given room can arrive from several directions at once instead of trickling down one long, skinny pipe.

The catch is resistance. Every wire has some, and when millions of cells draw current through it, Ohm's law bites: the voltage actually reaching a far-off cell sags below the ideal by V = I·R. This sag is called IR drop, and if the grid is too thin or too sparse, the local voltage droops enough that logic slows down or stops switching reliably — the far rooms get a weak dribble instead of full pressure. So PDN design is a balancing act: a denser, wider grid fights IR drop and electromigration, but it also steals metal tracks away from the signal wires that have to route through the same space.