floorplanning

Floorplanning is the very first move in physical design — the part you do before a single standard cell is dropped onto the silicon. Think of a city planner standing over an empty plot: before any house goes up, you decide how big the lot is, where the highways and the big landmarks (the stadium, the power station) go, and roughly where the water and electricity mains will run. On a chip you are doing exactly that. You fix the die and core area, you hand-place the big macros — SRAM blocks, PLLs, analog IP, anything too large or special to be auto-placed like an ordinary gate — you arrange the I/O pads or bump pins around the edge, and you sketch the power grid (the rings and straps that will feed current to everything). Only after this skeleton exists does the automated placer start filling the empty core with the millions of tiny logic cells.

Why sweat over it by hand? Because every automated step downstream inherits your decisions and cannot easily undo them. Put two chatty macros at opposite corners and the router will fight wire delay forever; cram cells in too tightly and there is no room left for clock-tree buffers or routing tracks, and timing closure becomes impossible. So you also reserve breathing room: a common starting target is a core utilization of roughly 60-75%, meaning the standard cells fill only that fraction of the core and the rest is left open for wiring, buffering, and clock trees added later. Macros get keepout halos so cells don't crowd their pins, and you add placement blockages where you want the placer to stay out. A good floorplan makes placement, clock-tree synthesis, and routing flow almost on their own; a bad one quietly poisons every signoff check that follows.