Physical design

placement

Placement is the step where every standard cell finally gets a home. After floorplanning has carved out the core area and laid down the rows — long horizontal stripes, one cell-height tall, with power and ground rails along their edges — placement decides which (x,y) spot each cell lands in. Picture seating a few million guests in a stadium: you can't just drop them anywhere. Cells that chat constantly (a flip-flop feeding the gate next to it) want adjacent seats so their connecting wire stays short and fast; spread them across the die and the wire delay alone can blow your timing. So the tool isn't just packing boxes — it's solving a giant optimization that trades off wirelength, timing, and how crowded each region will get once the router shows up.

It happens in stages. Global placement is the rough first pass: an analytical engine (think of it as modeling the connections as springs and letting everything relax toward a low-energy spread) finds an approximately ideal position for each cell, steering away from timing-critical stretches and congested hot spots. At this point cells are allowed to overlap and sit slightly off the legal grid — it's a sketch, not the final seating chart. Detailed placement then refines that sketch locally, swapping neighbors, sliding cells, and resizing or buffering to recover the last picoseconds of timing. Finally legalization snaps every cell down onto a legal site — the discrete grid positions the rows allow — so that no two cells overlap and each sits cleanly on the row pitch, ready for clock tree synthesis and routing to come next.

Density matters here: the placer watches the utilization ratio, the fraction of the core area your cells actually consume. Push it too high and there's no room left for the wires the router still has to thread, so congestion explodes; leave it too low and you've wasted silicon you paid for. Good placement quietly sets up everything downstream — a sloppy one hands routing and timing closure a mess they may never fully dig out of.

utilization = total cell area / available core area (e.g. 0.70 means 70% full, leaving ~30% for routing)

Placement targets a utilization that fits the cells while leaving enough open area for the router to thread wires without congestion.

Placement only positions logic cells and leaves clock and signal wires for later; the clock network in particular is built afterward by clock tree synthesis, not during placement.

Also called
cell placementglobal placementdetailed placementlegalization单元布局详细布局合法化單元佈局詳細佈局合法化