Low-power design & UPF

isolation cell

An isolation cell is a guard placed on every wire that leaves a block which can be switched off, holding that wire at a known, safe value while the block sleeps. When you power down a domain, its outputs don't snap cleanly to 0 — they float to indeterminate, drifting voltages, like a door left swinging in the wind. Any still-powered logic downstream would read garbage and, worse, sink wasteful short-circuit current. The isolation cell slams that door shut and pins it to a defined level.

Mechanically it is usually a simple AND or OR gate inserted on the boundary net, driven by an isolation-enable signal: assert the enable just before powering down, and the output is clamped to 0 (AND) or 1 (OR) regardless of the now-dead block. Crucially the isolation cell and its enable logic must live in an always-on power domain — if the guard itself loses power, there is nothing holding the door. UPF/CPF lets the designer declare the clamp value, the enable signal, and which boundary nets need isolating, and the tool inserts the cells automatically.

Order matters: the isolation-enable must assert before the power switch turns off and de-assert only after the block is fully powered and reset — the power-up/down sequence is part of the verified power intent.

Also called
clamp cellisolation gate隔離閘箝位單元