Low-power design & UPF

power domain

A power domain is a region of a chip whose logic shares one common power-supply condition — the same voltage, and the same on/off and sleep behaviour. Think of a big office building wired into separate electrical zones: the lobby stays lit all night, but each floor has its own breaker so the cleaning crew can switch off floors nobody is using. The chip is the building; each power domain is a floor with its own breaker.

Partitioning a design into power domains is the foundation of all power management. One domain might run the always-on real-time clock at a low voltage; another runs the CPU at full voltage but gets switched off entirely in sleep; a third runs at a boosted voltage for the GPU. Whenever a signal crosses from a domain at one voltage to a domain at another, it must pass through a level shifter, and whenever it leaves a domain that may be switched off, an isolation cell clamps it to a safe value. Tools learn the boundaries and rules of every domain from a power-intent file.

A simple three-domain SoC partition.

Power domains are described in UPF/CPF as named objects; a single domain can still contain a switched (gated) region plus an always-on region for things like isolation control and retention.

Also called
voltage area電源領域電源區域