Fault coverage

Fault coverage is the single number that says how good your test is: of all the faults in the model's list, what fraction can your patterns actually detect? If a circuit has 1,000,000 stuck-at faults and your patterns catch 985,000 of them, your fault coverage is 98.5%. It is the headline grade on a test program — and the gap between it and 100% is the population of defective chips that could slip through testing and reach a customer.

Why not always demand 100%? Some faults are genuinely untestable (redundant logic, unused nodes) and rightly excluded, giving a related metric called test coverage. But the last fraction of a percent is also the hardest and most expensive to win, requiring extra patterns or DFT structures. The stakes scale with the application: consumer parts may ship at ~99% stuck-at coverage, while automotive and medical chips chase 99.9%+ across multiple fault models because an escape — a defective chip that passed test — can become a recall, a crash, or a death. The famous link is that higher coverage drives down defects-per-million (DPM) shipped.