Test pattern (test vector)

A test pattern is one concrete stimulus-and-expected-response pair that the tester applies to a chip: 'drive these inputs to these values, clock the chip, and the outputs should read exactly this.' If the real chip's outputs match, that pattern passes; if even one bit differs, the chip fails and is binned out. A full test program is just an ordered stack of thousands of such patterns, each one designed by ATPG to corner a particular set of faults.

In a scan-based flow, a pattern has a shape: shift a bit-stream into the scan chains, apply any primary inputs, pulse the capture clock, then shift the captured response out while comparing it against the golden expected values. Because shifting a long chain takes many cycles, patterns are expensive, and a huge effort — test compression — goes into encoding the same fault coverage in far fewer patterns and far fewer scan-pin cycles, sometimes shrinking test data and test time by 10–100×.