ATPG (automatic test pattern generation)

ATPG is the algorithm — and the tool running it — that automatically invents the input patterns needed to expose every modelled fault in a chip. Given a list of, say, ten million possible stuck-at faults, ATPG asks for each one: what bits must I set, and what must I observe, to make a good chip and a faulty chip give visibly different answers? Solving that for one fault is a small logic puzzle; ATPG solves it millions of times and then cleverly merges patterns so one test vector kills many faults at once.

Working through scan chains, ATPG produces a compact set of scan-in vectors plus the expected scan-out responses. The art is efficiency: detecting more faults with fewer patterns means less time on the expensive tester, so ATPG packs unrelated faults into the don't-care bits of existing patterns. The result is reported as fault coverage — the percentage of the fault list the patterns actually catch — and a residue of 'untestable' or 'aborted' faults the tool could not justify or that have no possible test.