Fault model

A fault model is a simplified, mathematical caricature of how a physical defect shows up as wrong logic behaviour. Real silicon can fail in endlessly messy ways — a hairline crack, an under-etched via, a stray particle — but a tester cannot reason about cracks; it reasons about 0s and 1s. A fault model is the bridge: it says 'whatever the physics, treat the effect AS IF a specific node is stuck, or a transition is too slow, or two wires are shorted', giving the test tools a finite, well-defined list of things to hunt for.

Different models catch different real defects. The stuck-at model catches gross opens and shorts. The transition (or at-speed) model catches parts that work slowly — fine at the test bench but failing at full clock speed. The bridging model catches two wires accidentally welded together; IDDQ watches abnormal leakage current; and cell-aware models go inside the standard cell to catch intra-cell defects. Test engineers run patterns for several models, because no single caricature captures every way silicon can betray you.