dynamic voltage and frequency scaling (DVFS)

DVFS lets a chip change its own clock speed and supply voltage on the fly to match how hard it currently needs to work — like a car that drops to a gentle idle in a car park and floors it on the motorway. When your phone is just showing a static screen, its CPU coasts at a low voltage and frequency sipping power; when you launch a game, it ramps both up to deliver burst performance, then eases off again.

The payoff is huge because of physics: dynamic power scales with V²·f, so a small voltage cut yields an outsized energy saving. Crucially, a slower clock allows a lower voltage (gates have more time to settle), and dropping voltage saves quadratically while dropping frequency only saves linearly — so they are scaled together along a curve of valid voltage-frequency operating points. A power-management controller picks the point each instant based on workload and temperature. The hard part is that gate delay rises sharply at low voltage, so timing must be re-verified (signed off) at every operating corner the chip is allowed to use.