phase-locked loop (PLL)

A phase-locked loop is a feedback loop that doesn't watch a voltage or a current — it watches phase, the timing of a clock's edges. Picture a drummer (your generated clock) trying to stay perfectly in step with a metronome (a reference clock). A phase detector listens to both and reports who's ahead and by how much; that error nudges the drummer to speed up or slow down until the two are marching together. When the drummer's edges hold a fixed timing relationship to the metronome's, the loop is locked.

Concretely, the chain is: a phase/frequency detector compares the reference against a fed-back copy of the output; a charge pump turns each early/late verdict into a little squirt of charge; a loop filter smooths that into a slow control voltage; that voltage drives a voltage-controlled oscillator (VCO) whose frequency rises and falls with it; and a divide-by-N counter feeds the VCO's output back to the detector. Because the loop forces the divided-down output to match the reference in phase and frequency, the output ends up at N times the reference — fout = N x fref. That's how a clean but slow crystal at, say, 50 MHz becomes a 5 GHz on-chip clock.

Two jobs fall out of that one mechanism: multiplication (pick N) and cleanup. The loop is a control system, so it has a bandwidth and a stability budget just like an op-amp — you watch phase margin so it locks smartly instead of ringing. Inside the loop bandwidth the output tracks the reference and the loop suppresses the VCO's own wander; outside it, the VCO runs free and the reference's noise is filtered away. Where you set that crossover is the central design tradeoff, because it decides how much jitter survives at the output.