Data converters & PLLs

jitter

A clock is supposed to tick at perfectly even intervals, but no real clock does. Jitter is the small, restless wobble in when each edge actually arrives — a few picoseconds early here, a few late there. If voltage noise is the fuzz you see when you zoom in on a signal's vertical axis, jitter is that same noise smeared along the horizontal (time) axis: the time-domain cousin of noise. Picture a drummer who means to play dead-on the beat but drifts a hair ahead or behind each hit — the song still plays, but the timing isn't crisp, and anyone trying to dance in perfect lockstep starts to stumble.

Jitter comes in two flavors. Random jitter is born from physics that never stops — thermal noise and flicker (1/f) noise inside the oscillator and buffers — so it has no upper bound and its spread grows the longer you wait between a reference edge and the one you're measuring. Deterministic jitter is bounded and has a cause you can usually name: power-supply ripple, crosstalk from a neighbor, or data-pattern effects on a link. Engineers slice it further into period jitter (how much one cycle's length varies), cycle-to-cycle jitter (the change from one period to the very next), and long-term or phase jitter (accumulated wander over many cycles). Phase jitter is really just the integral of an oscillator's phase noise — the same imperfection viewed in the time domain instead of the frequency domain.

Why it matters: jitter sets two hard ceilings. On a high-speed serial link, every picosecond of timing uncertainty narrows the horizontal opening of the eye diagram, so the receiver has a smaller window to decide whether a bit is a 1 or a 0 — push the data rate up and jitter is often what caps it before voltage noise does. In a data converter, the moment you sample is set by a clock edge, so a jittery edge samples a fast-moving input at slightly the wrong instant, injecting an error that grows with input frequency. That single effect places a firm upper bound on a converter's achievable SNR, no matter how many bits the architecture promises.

SNR(jitter-limited) = -20*log10(2*pi*f_in*t_jitter)

The SNR ceiling an ADC hits from clock jitter alone: a 1 GHz input sampled with 1 ps RMS jitter caps SNR near 44 dB (about 7 effective bits), which is why fast converters live or die by their sampling clock.

Jitter and phase noise describe the very same imperfection — jitter is the time-domain RMS view, phase noise is the frequency-domain (dBc/Hz) view — so a low-phase-noise reference and a low-jitter clock are two names for the same goal.

Also called
timing jitterclock jitteraperture jitter