RTL & verification

Verilog

Verilog is the most widely used hardware description language (HDL) — a text language for describing digital circuits rather than writing step-by-step instructions. You declare a `module` with inputs and outputs and then say, in code, how the outputs depend on the inputs. A tool later turns that description into real gates.

The crucial mental shift is that Verilog is not a programming language. Lines do not run one after another; they describe hardware that all exists and reacts at the same time. An `assign` statement is a permanent wire, not a one-time calculation, and an `always @(posedge clk)` block describes flip-flops that all update together on each tick of the clock.

Most modern projects use SystemVerilog, a superset that adds richer types and verification features, but engineers still say "Verilog" for both.

module mux2(input a, b, sel, output y);
  assign y = sel ? b : a;   // a 2-to-1 multiplexer in one line
endmodule

A 2-to-1 multiplexer described in Verilog.

Also called

HDLSystemVerilog硬件描述语言硬體描述語言