Timing closure & STA

Multi-corner multi-mode (MCMM)

Multi-corner multi-mode is the recognition that a chip must keep correct timing not in one situation but in dozens at once — every combination of operating condition (a corner) and operating mode (a function). A corner captures the physics: a slow-process / low-voltage / high-temperature corner makes gates sluggish (the setup nightmare), while a fast-process / high-voltage / low-temperature corner makes them race (the hold nightmare). A mode captures intent: full-speed mode, low-power mode, scan-test mode, sleep mode — each can use a different clock and different constraints.

Cross those two lists and you get a grid of scenarios — often 20 to 100+ — and timing must close in every cell of the grid simultaneously, because the silicon will eventually live through all of them. Fixing a path in one scenario must not break it in another, which is why modern tools analyze and optimize all scenarios concurrently rather than one at a time. MCMM is the reason a seemingly small design can take days of compute and weeks of engineering to sign off.

Timing must be clean in every corner×mode cell at once.

To tame the explosion, engineers identify a 'dominant' subset of scenarios that bound all the others, but picking the wrong dominant set is a notorious way to miss a silicon failure that only shows up in a corner you skipped.

Also called
MCMMmulti-mode multi-corner多模多角