Timing derating
Derating is a deliberate fudge factor applied to delays to account for the fact that no single number is ever exactly right — neighbouring gates that should be 'identical' actually vary a bit across a chip, and STA must protect against the unlucky combination. The tool multiplies path delays by a derating factor: it pads data-path delays to be a little longer and clock-path delays to be a little shorter (or vice versa) so that the gap it checks is pessimistically wide. It's the engineering equivalent of leaving early for the airport because traffic might be bad.
Crude flat derating (classic OCV) applies the same percentage everywhere and is wastefully pessimistic. Smarter schemes — advanced OCV (AOCV) and parametric OCV (POCV/SOCV) — scale the penalty with how many stages a path has and treat variation statistically, because random local mismatch partly averages out over a long path. Getting derate right is a high-stakes balancing act: too little and the chip fails in the field; too much and timing 'closure' becomes impossibly hard and the design is needlessly slow.
Derating and on-chip variation describe the same physical worry from two sides: OCV is the phenomenon (delays vary locally), derating is the cure (apply margin) — POCV's statistical √N scaling is why modern signoff is far less pessimistic than 10-year-old flat-derate flows.