Clock uncertainty

Clock uncertainty is a single guard-band number that lumps together everything that makes the clock edge fuzzy rather than razor-sharp — jitter from the PLL, skew that hasn't been built yet, modeling inaccuracy, and a pad of safety margin. Before the clock tree is physically built, the timing tool has no real skew to work with, so engineers pre-load an uncertainty value that pessimistically pretends the clock could land anywhere within a small window. It's like padding every appointment with 'give or take ten minutes' because you don't yet know the exact traffic.

Mechanically, uncertainty is subtracted from the available time in a setup check (making the deadline earlier and the path harder) and can be applied to hold checks too. Crucially, its value usually shrinks as design progresses: a big pre-CTS uncertainty (which stands in for unbuilt skew) is replaced after clock tree synthesis by real, computed skew plus a much smaller residual for jitter and margin. Setting it too high needlessly over-constrains and bloats the design; too low and you ship a chip that fails when the real clock wobbles.