a SIMD extension
Picture a car that ships with a normal engine, and later the maker sells a bolt-on turbo kit that adds extra power for people who need it — but cars without the kit drive perfectly fine, just slower on the highway. A SIMD extension is a turbo kit for a CPU's instruction set: a bundle of extra instructions and wide registers added to an ordinary scalar ISA so that code which wants data-level parallelism can use it, while old code keeps working untouched.
These extensions arrived because everyday CPUs, not just supercomputers, started doing array-heavy work — decoding video, mixing audio, rendering images, running game physics. So vendors grafted vector-style instructions onto mainstream ISAs. On x86 the family grew over decades: MMX, then SSE (128-bit), then AVX (256-bit), then AVX-512 (512-bit), each a new extension adding wider registers and more operations. On ARM the equivalents are NEON and the scalable SVE. Each extension defines new register names (XMM, YMM, ZMM on x86) and new instructions that pack several numbers per register and operate on them in lockstep, exactly the SIMD idea.
The honest, important subtleties. First, a SIMD extension is part of the architecture — the contract software sees — so a binary compiled for AVX-512 will crash or refuse to run on an older chip that lacks those instructions; programs must check at runtime which extensions the CPU supports, or ship multiple versions. Second, having the hardware is not the same as using it: the operations exist, but your loop only benefits if it is written or compiled to feed those wide lanes (see auto-vectorization). Third, aggressive use of the very widest units (AVX-512) historically made some chips lower their clock frequency to stay within power limits, so wider is not always a clean win — a real reminder that more SIMD width is a tool, not a guarantee.
A program built for AVX2 uses 256-bit YMM registers to add eight floats per instruction. Run that same binary on a 2008 CPU that only has SSE (128-bit) and it hits an illegal-instruction fault — the AVX opcodes simply do not exist there, which is why software probes CPU feature flags (CPUID) before using them.
A SIMD extension adds wide registers and instructions to a scalar ISA; using them requires the chip to actually support that extension.
A SIMD extension is part of the ISA, so it breaks binary compatibility: an AVX-512 binary will not run on a chip without AVX-512. And merely having the unit does not speed your code up — the code must actually be vectorized to use it.