a vector register
An ordinary register is like a single mailbox that holds one number. A vector register is a row of mailboxes welded together and addressed by one name — open it and you find not one number but a whole list of them, say 32 floating-point values sitting side by side. When an instruction names that register, it is reaching for all of them at once.
Physically, a vector register is a wide bank of storage divided into equal slots called elements or lanes. A 512-bit vector register can hold sixteen 32-bit numbers, or eight 64-bit numbers, or thirty-two 16-bit numbers — the same bits, sliced into different lane widths depending on the instruction. A vector operation reads two such registers, pairs up lane 0 with lane 0, lane 1 with lane 1, and so on, runs the operation in every lane, and writes the results into a third vector register. The lanes are independent, so they all compute at the same time. To and from memory, a single vector load fills the whole register from a contiguous run of memory, and a vector store writes it all back.
Vector registers are the visible heart of any SIMD or vector machine — in x86 they are the XMM, YMM, and ZMM registers (128, 256, and 512 bits) of the SSE/AVX families; in ARM they are the NEON and SVE registers. The number and width of these registers is part of the instruction-set architecture, which is why widening them (SSE to AVX to AVX-512) creates a new instruction-set extension and old binaries cannot use the new width until recompiled. The catch is that filling a vector register pays off only if you have enough adjacent, independent data to fill it; a half-empty vector register wastes lanes.
A 256-bit AVX register (YMM) holds eight 32-bit floats. Load eight array elements into YMM0 and eight more into YMM1, issue one vaddps, and YMM2 now holds the eight element-wise sums — all eight additions done by one instruction over one cycle's worth of lanes.
One named register, many lanes inside it; the operation hits every lane in parallel.
The width of a vector register is part of the ISA, not a free knob. AVX-512 code will not run on a chip that only has 256-bit registers; you must recompile, and a half-filled vector register leaves lanes idle.