Frontiers & the Post-Moore Era

RISC-V as an open standard

/ RISC-V = 'risk five' /

RISC-V (say 'risk five') is the most prominent real example of an open instruction set architecture. The name says two things. RISC means it is a Reduced Instruction Set Computer — a clean, simple, load-store style of vocabulary in the tradition that strips instructions down to a small, regular core. The 'V' is the Roman numeral five, marking it as the fifth such design from the Berkeley research lineage. It began as a teaching and research ISA at the University of California, Berkeley, around 2010, and grew into a free, public standard now stewarded by a non-profit foundation rather than any single company.

Its defining design choice is modularity. RISC-V is built as a tiny mandatory base — just the bare bones of integer arithmetic and control flow, in a 32-bit or 64-bit word size — plus a menu of optional, standardized extensions you bolt on as needed: one for multiply and divide, one for floating point, one for atomic operations, one for compressed instructions, one for vectors, and so on. A simple sensor chip might implement only the small base; a server processor adds many extensions. Every conforming implementation runs the same base software, so the ecosystem of compilers, operating systems, and tools is shared across wildly different chips. This 'small core plus opt-in extensions' shape is exactly what a single corporate owner of an ISA tends to resist, and what openness makes natural.

Why does an open standard reshape the whole industry? It lowers the barrier to building a processor from a costly license negotiation to a free download, so universities, startups, large companies, and national programs can all design compatible chips. It concentrates the world's effort onto one shared software base instead of fragmenting it. And it lets anyone add a custom extension for a specialized job — exactly the kind of specialization the post-Moore era demands. The honest caveat is that being open does not by itself make a chip fast or mature: a RISC-V core is only as good as its microarchitecture and its software ecosystem, both of which take years of investment to rival entrenched incumbents.

A tiny RISC-V microcontroller in a smart thermostat might implement just 'RV32I' — the 32-bit integer base, about 40 instructions. A datacenter RISC-V chip implements RV64I plus the M (multiply/divide), A (atomic), F and D (floating point), C (compressed), and V (vector) extensions. Both run software built with the same RISC-V compiler toolchain.

A small mandatory base plus opt-in extensions: the same standard scales from a sensor to a server.

Open does not mean automatically best. RISC-V removes the license barrier, but a competitive chip still needs a strong microarchitecture and a mature software ecosystem — both of which take years to build. Openness is an enabler, not a performance guarantee.

Also called
RISC-Vthe RISC-V ISARISC-V 開放標準第五代精簡指令集