a load-store architecture

A load-store architecture is an ISA built on one strict rule: only special load and store instructions may touch memory, and everything else works purely on registers. It is like a kitchen rule that says you may only cook with ingredients on the counter — to use anything from the pantry you must first carry it out (a load), and to put a finished dish away you must carry it back (a store). You can never stir a pot that is still sitting in the pantry.

In practice this means an arithmetic or logic instruction reads its inputs from registers and writes its output to a register; it has no way to name a memory location at all. So a calculation on values that live in memory always follows the same three-beat rhythm: load the values into registers, compute on the registers, store the result back to memory. RISC-V and MIPS are textbook load-store architectures; this design is one of the defining traits of RISC.

Why impose such a restriction? Because memory is far slower and more variable than registers, confining all memory access to two well-understood instruction types makes the whole machine simpler, more regular, and easier to pipeline at high speed — the hardware always knows exactly which instructions might stall waiting for memory. The honest contrast is a 'register-memory' (or 'memory-memory') architecture, the CISC style, where an instruction like x86's 'add' can read an operand straight from memory, do the math, and even write back to memory in one instruction. That is more convenient and denser, but each such instruction hides a memory access inside it, which complicates fast implementation.