an addressing mode
An addressing mode is a rule for how an instruction names where its data comes from. Think of the different ways you can tell a courier where to deliver: 'hand it to the person in office 6' (use a register's value), 'here is the actual item' (an immediate constant), or 'go to the address on this note, then walk three doors down' (a base address plus an offset). Each is a different addressing mode, and the ISA defines exactly which ones it supports.
RISC-V keeps the list short and simple, which is very much in the RISC spirit. Register addressing means the operand is the value in a named register. Immediate addressing means the operand is a constant carried in the instruction. Base-plus-displacement (also called base-plus-offset) addressing, used by loads and stores, forms a memory address by adding a small constant displacement to a base register's value — perfect for reaching field 8 inside a structure whose start is in a register. PC-relative addressing, used by branches and some jumps, forms a target address by adding an offset to the program counter, so the same code works no matter where in memory it is loaded.
Addressing modes matter because they decide how naturally common patterns map to single instructions. Base-plus-displacement makes array and structure access one clean step; PC-relative addressing is what makes code relocatable. Here is an honest contrast that goes to the heart of RISC versus CISC: CISC ISAs like x86 offer many elaborate modes (for example 'base register plus index register times a scale plus a displacement' all computed in one instruction), which packs more work per instruction but makes each instruction more complex to decode and execute. RISC deliberately offers few, simple modes and lets the compiler combine plain instructions instead.
To read element i of an integer array whose base is in x10, a compiler computes the offset (i times 4 bytes) into x5, adds it to the base, then uses base-plus-displacement: 'lw x6, 0(x5)'. The displacement here is 0; the address came from the base register.
Base-plus-displacement turns 'the element at offset N from here' into one load.
RISC-V's small set of addressing modes is a feature, not a limitation. Rich CISC modes do more per instruction but cost decode and execution complexity — the trade-off at the heart of RISC versus CISC, not a sign one is simply better.