RISC-V

RISC-V (pronounced 'risk-five') is a modern instruction set architecture used throughout this domain as the teaching example, the way a beginner cookbook keeps coming back to one well-chosen recipe. It is a clean, simple design from the early 2010s at the University of California, Berkeley, and it has two qualities that make it perfect for learning: it is small and regular (so you can hold the whole thing in your head), and it is open and free, meaning anyone can build a chip for it or read the full specification without paying a license fee.

RISC-V is a load-store, RISC-style ISA. That means instructions are simple and do one thing each, most are a fixed 32 bits wide so they line up neatly, and only two special instructions — load and store — actually touch memory; all arithmetic happens between registers. A basic RISC-V chip has 32 integer registers named x0 to x31 (where x0 is permanently zero) plus the program counter. The core is deliberately tiny, and richer features (floating point, vectors, compressed instructions) are added as separate, optional extensions, so a small embedded chip and a big server chip can both be 'RISC-V' while including different pieces.

Its closest classic cousin is MIPS, an older teaching ISA it strongly resembles, so much of what you learn here transfers. RISC-V matters in the real world too, not just the classroom: because the standard is open, startups, universities, and giant companies can design RISC-V cores without negotiating with a single owner, which is reshaping who gets to build chips. A small honesty note: 'open ISA' means the specification is free to use; it does not mean every RISC-V chip's internal design is public — companies still keep their own microarchitectures secret.