physical verification
Once your layout is placed, routed, and timing-clean, physical verification is the final inspection that asks one blunt question: can this actually be built, and is it really the circuit you meant to build? Think of it like a building inspector walking a finished house before anyone moves in. The blueprints might be beautiful, but the inspector checks that the walls are far enough apart to meet code, that the wiring actually connects the switches to the lights you drew on the plan, and that nothing was left in a state that will quietly catch fire later. Physical verification is the umbrella name for that whole inspection pass, and a layout has to come out clean on every check before it can go to the foundry for tapeout.
It bundles three families of checks. Design rule check (DRC) confirms the geometry obeys the foundry's manufacturing rules — minimum spacing between wires, minimum metal width, enclosure of vias, density of each layer — the dimensional code that keeps the shapes printable on silicon. Layout versus schematic (LVS) traces every wire and device in the drawn layout and proves it matches the intended netlist transistor-for-transistor and net-for-net, so a swapped connection or a missing device gets caught instead of shipping. The third family is electrical rule checks: antenna rules, which make sure long stretches of metal connected to a transistor gate during fabrication can't accumulate enough charge to blow that thin gate oxide, plus broader ERC checks for things like floating gates or shorted power and ground. Only after DRC, LVS, and the antenna/ERC checks all report zero violations is the GDSII (or OASIS) database considered signed off.
The reason engineers treat a single leftover violation so seriously is economics, not pedantry. A photomask set and a fabrication run cost a fortune and take weeks to months; if a real DRC or LVS error slips through, the silicon that comes back can be dead or wrong, and fixing it means a respin — re-doing masks and re-fabricating — that burns months of schedule and a great deal of money. That is why physical verification is non-negotiable and why a clean run is the literal gate to tapeout.
Tapeout signoff is an AND of all three check families — any single non-waived violation blocks the release.
Some DRC 'errors' are known false flags or approved waivers, but every one must be explicitly reviewed and signed off — never silently ignored — because the tool can't tell a safe waiver from a real defect.