design rule check (DRC)

Picture a building inspector walking a finished construction site with the city code in hand: walls must be at least so thick, stairs no steeper than a limit, exits a minimum width apart. A design rule check is that inspector for your chip layout. The foundry hands you a rule deck — hundreds of geometric requirements its manufacturing line can actually print and etch reliably — and a DRC tool sweeps every polygon on every layer to confirm none of them break the code: each wire is at least the minimum width, no two shapes sit closer than the minimum spacing, every shape clears the minimum-area floor, and metal must overlap (enclose) the via beneath it by a set amount so the connection survives processing. The check is purely geometric. It asks 'can this be built?', not 'is the wiring correct?' — comparing your layout against the intended circuit is a separate step called layout-versus-schematic (LVS).

DRC runs late in the flow, after place-and-route has drawn the real metal, as part of physical verification (sometimes called signoff DRC, the foundry-blessed final pass). It rarely travels alone. Antenna rules ride alongside it: during fabrication, a long stretch of metal connected to a transistor gate can collect plasma charge mid-process and punch through the thin gate oxide, so the deck caps the ratio of exposed conductor area to the gate area it feeds — you fix a violation by adding a tiny protection diode or hopping the net up to a higher layer. An electrical rule check (ERC) is the sibling that hunts electrical mistakes geometry alone won't reveal, such as floating gates or a node shorted between power and ground. Clean DRC, clean LVS, clean antenna and ERC together are the gate you must pass before a layout is allowed anywhere near tapeout.