layout versus schematic (LVS)

Once the layout is drawn, you have two pictures of the same circuit that have to agree. One is the schematic, or netlist — the intended wiring diagram that says which transistors exist and exactly which terminals connect to which nets. The other is the physical layout: a stack of colored polygons on different layers that, if you built it, would become the real silicon. LVS is the as-built-versus-blueprint check that asks one blunt question: does the thing you actually drew connect up the same as the thing you meant to draw?

A tool can't just eyeball polygons, so LVS first does device and connectivity extraction. It reads the layout layer by layer — where a poly stripe crosses a diffusion region it recognizes a transistor; where metal, contacts and vias touch, it stitches the pieces into one electrical net, threading up and down through the metal stack the same way current would. That gives a second netlist pulled straight from the geometry. LVS then compares the two netlists as graphs, matching devices and nets on both sides, and flags every place they disagree: a short (two nets that should be separate but got merged by a stray overlap), an open (one net that the layout accidentally split into two unconnected pieces), a swapped or mis-tapped connection, or a missing, extra, or wrong-type device. Many flows also do a parameter check, comparing each transistor's drawn width and length against what the schematic asked for.

LVS lives in the physical-verification stage, run alongside DRC after routing and before tapeout — DRC asks whether the geometry is manufacturable, while LVS asks whether it is the right circuit. A layout can be perfectly DRC-clean and still be wrong, because obeying spacing rules says nothing about whether net A actually reached the gate it was supposed to reach. Only when LVS reports a clean match do you trust that the silicon you ship will behave like the netlist you simulated and signed off on.