memory refresh

Picture those leaky water buckets from DRAM: left alone, a full bucket slowly drains until you cannot tell a 1 from a 0 any more. So a tireless attendant walks the rows on a fixed schedule, and for every bucket that is currently full, tops it back up to full — over and over, forever, just to stop the stored data from quietly evaporating. Memory refresh is that endless topping-up performed on every DRAM cell.

Concretely, DRAM cells lose their charge in milliseconds, so the system must refresh each row within a fixed window (commonly every 64 milliseconds, or 32 ms in hotter conditions). Refreshing a row means reading its contents into the row buffer (which restores full charge as a side effect of sensing) and writing them straight back. The memory controller or the chip's internal logic steps through all rows, refreshing them on a rolling schedule so that no cell ever goes too long unrefreshed. Because reads are sensed and rewritten anyway, every ordinary access also incidentally refreshes the row it touches.

Why it matters and the honest cost: refresh is pure overhead — time and energy spent not to compute anything, but merely to keep memory from forgetting. While a row is being refreshed it cannot serve a normal request, so refresh steals a small slice of bandwidth (a few percent), and that slice grows as chips get denser with more rows. This is one of DRAM's intrinsic taxes, and it is exactly what SRAM avoids — SRAM never needs refresh because its bits are actively held.