a DRAM bank

Imagine a giant library split into several independent reading rooms, each with its own librarian and its own single open desk. To read a book in a room you first fetch it from the shelves onto that room's desk; while it sits on the desk you can flip to any page instantly. The rooms work in parallel — librarian A can fetch a new book while librarian B is still reading from their desk. A DRAM bank is one such independent reading room inside a DRAM chip.

Concretely, a DRAM chip is divided into several banks (commonly 8 to 32), and each bank is a 2-D grid of cells addressed by a row and a column. Each bank has exactly one row buffer — its single 'open desk.' To access data you first activate a row, which copies that entire row of cells into the bank's row buffer (the slow row-access step); then you read or write specific columns out of that buffer (the fast column-access step). Crucially, each bank has its own row buffer and can be in a different state, so several banks can have rows open and be servicing requests at the same time.

Why it matters: banks are the source of bank-level parallelism, the main trick for hiding DRAM's long latency. While one bank is busy doing a slow row activation, the memory controller can fire requests at other banks, overlapping their work so the memory system stays busy. The honest limit is the single row buffer per bank: two requests to different rows of the same bank conflict — the open row must be closed and a new one activated, paying the full row-access penalty. Spreading accesses across banks is what keeps memory fast.