logic simulation
Before a chip exists as silicon, you can still "run" it — as a program. Logic simulation takes your HDL description of a design, plus a testbench that pokes its inputs, and computes what every wire and register does, moment by moment, as a fake clock ticks forward. You're not running the design on hardware; you're running a model of it on your laptop, and watching the results.
Concretely, the simulator advances a notion of simulated time and re-evaluates the design only where something changes. Drive an input high, and it propagates that edge through the logic, schedules the downstream gates and flip-flops to update at their proper delays, settles everything for that instant, then moves on to the next event. This event-driven loop is why even a short span of real chip behaviour can take far longer to simulate — every signal transition is bookkeeping the tool must track explicitly. The payoff is total visibility: you can dump every node to a waveform and scrub through time to see exactly when and why a signal went wrong.
The same flow runs at different levels of fidelity. Early on you simulate RTL — fast, and focused purely on whether the logic is functionally right. Later, after synthesis, you can simulate the gate-level netlist with back-annotated cell delays to confirm the netlist still behaves correctly — catching things like reset and unknown-value (X) problems that RTL can hide. But simulation isn't how you prove timing is met; that's the job of static timing analysis. What simulation answers is one question — does it do the right thing? — which is why it's the backbone of design verification long before tape-out.
`timescale 1ns/1ps initial begin clk = 0; forever #5 clk = ~clk; // toggle every 5 time units -> 10 ns period -> 100 MHz end
With a `1ns` time unit, toggling every `#5` gives a 10 ns period — a simulated 100 MHz clock. But `#5` means "wait 5 time units," not 5 real nanoseconds on any chip; the frequency is whatever the timescale makes it.
"Passing simulation" only means the design did the right thing for the stimulus you happened to apply — it's evidence, not proof. Coverage metrics and formal verification exist precisely because no realistic testbench can exercise every possible input sequence.