testbench
Before you trust a new circuit design, you want to put it on the bench, hook up a signal generator to its inputs, and watch its outputs on a scope — feeding it inputs you control and confirming it does the right thing. A testbench is that bench, written in code. It is a piece of HDL that surrounds your design — the design under test (DUT) — drives stimulus into its inputs, and inspects what comes back out, all in simulation, with no physical hardware involved.
The defining trait of a testbench is that it is not synthesizable: it never becomes gates on a chip. That freedom is the whole point. Where your design is restricted to constructs that hardware can actually build, a testbench can use file I/O, `wait` statements, delays in nanoseconds, loops, and printed messages — whatever it takes to mimic the outside world and to judge the design. A typical testbench instantiates the DUT, generates a clock and reset, applies a sequence of inputs, and then checks each result — comparing the DUT output against an independently computed expected value and flagging any mismatch.
That checking is what separates a real testbench from a demo. A bench that only wiggles inputs and leaves you to eyeball waveforms catches almost nothing; a good one carries its own notion of "correct" — a reference model, a set of expected values, or assertions — and fails loudly the moment reality diverges. As designs grow, these benches scale up into full verification environments that pair self-checking with constrained-random stimulus to explore corners a human would never think to type by hand.
module tb;
reg [7:0] a, b;
wire [7:0] sum;
dut u_dut (.a(a), .b(b), .sum(sum));
initial begin
a = 8'd3; b = 8'd4; #10;
if (sum !== 8'd7) $error("got %0d, expected 7", sum);
$finish;
end
endmoduleA minimal self-checking testbench — declare the signals, drive known inputs, then assert the output matches the expected value.
"Testbench" borrows the lab-bench metaphor literally: in electronics a bench is the workspace where you probe and measure a device. The HDL version keeps the name even though the bench, the probes, and the device are now all just code.