Digital Logic & Building Blocks

a latch

A latch is the simplest circuit that can remember a single bit — the first place memory appears in hardware. The trick is feedback: take two gates and wire each one's output into the other's input, so they reinforce each other and hold whatever value they have settled into. It is like two people each insisting 'you said it first': the loop keeps the story alive even after the original prompt is gone. A latch stores one bit (a 0 or a 1) and keeps holding it until something deliberately changes it.

The classic SR latch is two cross-coupled NOR gates with a Set input and a Reset input. Pulse Set and the output locks to 1; pulse Reset and it locks to 0; with both inputs idle, the cross-coupling holds the last value indefinitely. A friendlier version is the gated D latch: it has a data input D and an enable input. While enable is high, the latch is 'transparent' — its output simply follows D; when enable goes low, the latch freezes and remembers whatever D was at that instant. So a D latch captures and holds a bit, controlled by the enable.

Why it matters and the catch: latches are the conceptual seed of all memory — flip-flops, registers, and SRAM cells all grow from this cross-coupled idea. But the plain latch is level-sensitive, meaning it stays transparent for the whole time enable is high, so its output can change repeatedly during that window. That makes timing in a feedback-rich circuit hard to reason about. The honest fix is the edge-triggered flip-flop, which captures its input at a single clock instant instead of over a whole interval — which is why synchronous designs are built mostly from flip-flops, not bare latches.

A push-on/push-off desk lamp behaves like an SR latch. Tap the 'on' switch and the lamp stays lit even after you let go — the state is held. Tap 'off' and it stays dark. The switch action is momentary, but the lamp remembers the last command. That persistence after the input ends is exactly what a latch contributes.

Two gates feeding each other hold a bit after the input is gone — feedback is the birth of memory.

A latch is level-triggered (active the whole time enable is high); a flip-flop is edge-triggered (active only at the instant the clock changes). Mixing them up is a classic source of timing bugs — the distinction is not a detail.

Also called
閂鎖SR latchD latch位準觸發鎖存器