synchronous design and setup/hold timing
Synchronous design is the simple, powerful discipline of letting one shared clock decide when everything happens. Instead of letting each part of a circuit update whenever its inputs happen to change — which in a sea of feedback and unequal gate delays would be chaos — every storage element updates only on the clock edge, all together. It is like a rowing crew obeying a single coxswain: nobody pulls on their own schedule, so the boat moves cleanly. Almost every chip you use is synchronous, because this shared heartbeat is what makes complex hardware predictable.
Between one clock edge and the next, here is the rhythm: at the edge, the flip-flops capture new state; their outputs then drive the combinational logic, which computes the next state; that result has until the next edge to settle; and on that next edge the flip-flops capture it. For this to be reliable, two timing rules must hold at each flip-flop. The setup time says the data input must stop changing and be stable a little before the clock edge. The hold time says it must stay stable a little after the edge. Together they define a small window around the edge during which the data must not move. If the combinational logic is too slow to settle before setup time, you get a setup violation — the data is sampled mid-change.
Why it matters: these timing rules connect logic to speed. The clock period must be at least the longest combinational delay between any two flip-flops plus the flip-flop's own delay plus setup time. That longest path is the critical path, and it sets the maximum clock frequency — you cannot clock faster than the slowest logic can settle. Violating setup is fixed by slowing the clock or shortening the path; violating hold (sampling data that arrives too early) cannot be fixed by slowing the clock and is a more dangerous bug. Get it wrong and a flip-flop can go metastable, hovering between 0 and 1 and producing unpredictable results.
Suppose the longest logic path between two flip-flops takes 0.8 nanoseconds to settle, the flip-flop adds 0.1 ns of its own delay, and setup time is 0.1 ns. The clock period must be at least 0.8 + 0.1 + 0.1 = 1.0 ns, so the maximum clock frequency is 1 / 1.0 ns = 1 GHz. Shorten that critical path and you can clock faster; nothing else helps.
The slowest path between flip-flops plus setup time fixes the minimum clock period — speed is a timing budget.
A higher clock frequency is not free speed. You can only raise the clock if the critical path settles in time; otherwise you get setup violations and wrong results. The 'megahertz myth' — assuming more GHz always means faster — ignores that real performance is instructions times cycles-per-instruction times cycle time.