UVM agent

A UVM agent is a self-contained, reusable bundle of verification components that knows how to talk to one interface of a design — say, one AXI bus, one SPI port, or one Ethernet MAC. Picture a translator-and-stenographer team assigned to a single diplomatic channel: one person speaks the protocol on your behalf (the driver), one writes down everything that crosses the wire (the monitor), and a supervisor decides what to say next (the sequencer). Bundle them together and you have an agent — drop it onto any testbench that has that interface and it just works.

Agents come in two flavours. An active agent drives stimulus (it has a sequencer + driver + monitor) and is used when the testbench must initiate traffic; a passive agent only watches (monitor alone) and is used when the design itself generates the traffic and you merely need to observe and check it. This reuse is the whole point of UVM: a company builds a verified PCIe agent once, then reuses it across every chip that has a PCIe port for the next decade.