Advanced verification & UVM

UVM sequence

A UVM sequence is a reusable recipe for stimulus — an ordered, parameterizable script that says 'generate these transactions, in this pattern, with these constraints.' Think of it as a screenplay rather than a single line of dialogue: 'reset the device, then do ten random writes, then a burst read, then deliberately violate the protocol.' The sequence describes intent at a high level and leaves the pin-level acting to the driver, so the same story can be replayed, randomized, and combined with others.

Sequences are where the creative test-writing happens, and they compose like Lego: a directed sequence pins down a specific scenario, a random sequence sprays constrained-random traffic to find the unexpected, and a virtual sequence orchestrates several agents at once to create cross-interface scenarios (e.g. 'flood the input port while the configuration bus reprograms a register'). This layering lets a small library of building-block sequences generate an enormous, mostly-automatic space of tests.

Sequences run on a sequencer but are not bound to it at compile time — the same sequence can run on any compatible sequencer, which is why sequence libraries port cleanly between projects.

Also called
sequenceuvm_sequencestimulus sequence激勵序列