UVM monitor

A UVM monitor is the passive observer that watches a design's interface and reconstructs, from the raw pin wiggles, what high-level transaction just occurred — then broadcasts that reconstructed transaction to anyone who cares. It is a court stenographer: it never speaks or interferes, it only records faithfully. Where the driver turns intent into pins, the monitor does the exact reverse: it turns pins back into meaning ('an AXI read of 0x10 returned 0x55'), publishing each one on an analysis port for scoreboards and coverage collectors downstream.

Keeping the monitor strictly passive is a discipline, not a suggestion: if the checking logic were inside the driver, the testbench would effectively be checking its own homework against its own assumptions. By rebuilding transactions independently from the wires — exactly as a real bus analyzer would — the monitor gives the scoreboard an honest, design-blind view of what actually happened on the bus, which is what makes the comparison trustworthy.